Systems and methods of utilizing multiple threads to facilitate parallel data copying to reduce an amount of time associated with backing up data. After traversing the protocol converting bridge the commands travel through the regular processor port. The chamber includes an exit aperture opposite the entrance aperture. The specific digital value is associated with the particular memory address received form the host. The process of charging and discharging the capacitor occurs during a predetermined time period and the number of times the capacitor switches during the time period represents the resistance of the memory element.