A nonvolatile semiconductor memory according to the present invention includes memory cell units, which include data select lines formed in parallel to each other, data transfer lines crossing the data select lines and aligned in parallel to each other, and electrically rewritable memory cell transistors disposed at intersections of the data transfer lines and the data select lines. All bids and the winners of both rounds are kept confidential until the second round is completed. The gain K3 of the second integrator 45 is set larger than the gain K3 of the first integrator 43. The memory access circuit is configured to, during a memory program operation, provide an inhibit voltage to the plurality of access lines. A second node is generated in the link hierarchy of query type. A wordline voltage controller determines the levels of wordline voltages to be supplied to the respective wordlines and a wordline voltage generator generates the wordline voltages at the determined levels.