The present disclosure provides a stream processor, an associated stream controller and compiler, and associated methods for data processing, such as image processing. The membrane includes a dense, gas impermeable layer and a first and second porous layer, wherein each of the first and second porous layers is a ceramic oxide material having a non-symmetrical load bearing skeleton of a plurality of pores having a graded porosity. A value of the temporal logic operator may be determined by a number of occurrences of an event during an existing activation of the first state associated with the temporal logic operator. In accordance with the data transfer method according to the present invention, the transfer of data between the memory devices included in the multi-memory chip is performed through the data transmission bus shared by the memory devices.