1459835834-f9e9f52a-8092-4d40-852c-d4d50bbc828b

A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. The special incentives may include providing a prize or award to frequent player program members that remotely use his or her membership. Integration of multiple devices in a common package ensures proper coordination and matching of the components, reduces the final product cost and reduces the physical space required on a telecommunications circuit for overvoltage and overcurrent circuit protection. A hydrophobic barrier exists between the regions, of this embodiment.