A PLL clock generator generates an output signal with a frequency N times as high as that of an input signal. With the entire surface of the chip irradiated with light ions, such as He ions, a lifetime killer is introduced from a position d2 shallower than a position d1 of a p-n junction surface, formed from the n\u2212-semiconductor layer and the p+-diffusion regions, to a position d3 deeper than the position d1 to form a short-lifetime region over the entire chip. The force F1 is applied to the boss in a direction that the collar separates from the armature core. This invention also relates to pharmaceutical compositions comprising such compounds. If the program was previously validly registered, then the transformation based on the diversity mechanism results in an executable program that will execute properly on the computer system; otherwise the transformation results in an executable program that will fail to correctly execute. The channel estimate may be generated from a long training symbol of the OFDM packet, and the additive noise power estimate and the SNR estimate may be generated from short training symbols of the OFDM packet.