A multi-level memory cell includes a substrate, an insulation layer, a silicon stripe, a first control gate, a second control gate, sourcedrain regions, silicon oxidesilicon nitridesilicon oxide composite layers. During the initial stages of a high-low transition, a control loop provides supplemental pre-charge to the gate of the switch transistor to reduce high-low switching delays. The isolator engine intercepts all the output operations of the application program attempting to send messages to the INTERNET. A voice message can then be left for the user of the system for anonymous contact. The appendage has a barb formed along the length while the slot has a notch formed along its length.