An electronic device can include a nonvolatile memory cell that includes a capacitor, a tunnel structure, a state transistor, and an access transistor. The processor acquires a touch coordinate detected on at least one of the electrostatic touch panel and the resistive touch panel and determines a touch mode including the presence or absence of strong touch at equal to or higher than a predetermined pressure based on the acquired touch coordinate. A cache line identified as cache bypass enabled is transferred to one or more higher level caches of the cache hierarchy, whereby a next higher level cache in the cache hierarchy is bypassed, while a cache line identified as cache bypass disabled is transferred to one or more higher level caches of the cache hierarchy, whereby a next higher level cache in the cache hierarchy is not bypassed.