The delay of delay circuit 10 is set within a predetermined range, and, in a stop mode, the clock pulses of 1 cycle of clock signal \u03c6in when transition is made from the stop mode to the DLL mode are excluded from the object detected by phase detector 20 such that phase difference \u0394\u03c6\u2032 detected by phase detector 20 is within a prescribed range when said transition is performed. Fittings are provided for releasably securing the profile light to the gantry and for releasably securing the profile light to the docking station. The recapturing of this otherwise wasted shoot-through current and gate charge allows for increased efficiency of the regulator.