A hermetically-sealed valve position indicator is provided with a valve control handwheel. Further, another object is to reduce writing voltage and erasing voltage while increase in the area of a memory transistor is suppressed. Physical alignment techniques are also described. At least partially gas-impermeable cover layer is provided on the diffusion barrier, at least from area to area. In a further embodiment, the cache also has a tag array including a first address input, a second address input, and a shared mode input, and a data array electrically coupled to the tag array and including a first address input, a second address input, and a shared mode input.