A time domain data converter with output frequency domain conversion. A bottom cover is disposed below the housing for covering the bottom opening. As a result, the time required to move wafer from the first position to the second position can be reduced. Additional systolic delay circuitry is provided for outputs of the adder, which are chained out to a second other instance of the DSP block circuitry. This is achieved by dividing the functionality of the AAL2 signaling protocol into a number of functional sublayers including an AAL2 Signaling Common Part, a Bearer Coordination Part and a Bearer Adaptor Part, wherein the BAP adjusts incoming and outgoing messages so that they are compatible with the AAL2 signaling protocol or the underlying signaling bearer service respectively.