1459915320-4a03fced-ec9b-4f3d-924d-f42fd177d30d

Capacitive coupling devices and methods of fabricating a capacitive coupling device are disclosed. The logic circuit receives a first signal indicative of whether the high-power, low write latency mode has been enabled, a second signal indicative of whether a row of memory cells in the memory device is active, a third signal indicative of whether the memory device is being operated in a power down mode, and a fourth signal indicative of whether read transmitters in the memory device are active. Preferably, the output is a vector-map showing the relationship between changes in overlay deviation values and changes in focus position of the substrate for the plurality of sets of marks.