In one embodiment, a processor comprises a plurality of instruction buffers, an instruction cache coupled to supply instructions to the plurality of instruction buffers, and a cache miss unit coupled to the instruction cache. The logic server dynamically controls the content of screens to be displayed on the display. The reconfigurable logic devices are reconfigurable to emulate a circuit design using at least one user clock to clock the logic elements and at least one signal routing clock to time multiplex the routing of emulation signals between the reconfigurable logic devices, with the at least one signal routing clock being independent of the at least one user clock. The circumferential extent of the first chamber is greater along a portion for applying force to the ring in a second pivotal direction than along a portion for applying force in the first pivotal direction such that a net force is applied in the second pivotal direction.