A method of manufacturing a twin-ONO-type SONOS memory using a reverse self-alignment process, wherein an ONO dielectric layer is formed under a gate and physically separated into two portions using a reverse self-alignment process irrespective of photolithographic limits. In one example the cable includes a cable jacket defining an elongate cable core, a conductor assembly including four twisted pairs of conductors disposed along the core and a plurality of parallel elongate localized and like distensions in an inner surface of the cable jacket. The support and the oxide coating preferably have material compositions that differ from one another in coefficient of thermal expansion by no more than 5\xd710\u22126K. It matches common blocks of the S’s CFGs and T’s CFGs. The shielding layer further extends from the extension section to the stacking section. The comparing component generates an error signal based on the reference power signal and the calibrated power signal.