Hardware-based transactional memory mechanisms, such as Speculative Lock Elision, may allow multiple threads to concurrently execute critical sections protected by the same lock as speculative transactions. A data line is formed on the gate insulating layer, and a passivation layer is formed on the data line. The first-shaped units include peripheral first-shaped units. The injection angles include at least one of an upward tangential angle and a downward tangential angle.