A semiconductor device and method of generating clock signals where a phase lock loop, or a delay lock loop, comprises a duty cycle correction circuit having a shared charge pump and a plurality of amplification parts. The demodulator controls the RF_AGC and IF_AGC tuner gains according to an AGC characteristic of the tuner, to provide a constant level of the IF_OUT signal. The CPU executes dust correction processing based on the dust detection result during continuous document reading. The player is dispensed a specific prize ticket that is redeemable for the selected prize. A transitional layer covering the gate structure and the recess is deposited. A pixel unit movement vector generating unit generates a movement vector with a smallest error component between a frame signal of a current frame and a frame signal of an immediately preceding frame as a movement vector of a pixel.