Disclosed is a digital signal processing architecture for a flat panel display having non-uniform regions, which is not by means of materials, optical films or fabrication processes. The output device has the following elements. The free end of the bimetallic element is spaced apart form a trip lever and increasingly impinges the same in the direction of release was a result of the thermal deformation, the distance being adjustable by bending the bimetallic support. The test processor includes a high-speed test control circuit to adjust signal delay and supplies a test signal from the external terminal to the access terminal through the high-speed test control circuit when performing high-speed test at an actual operation speed. The BRC further includes a diode connected between a drain of each FET and a terminal of each GDC.