A path under test is selected from a semiconductor integrated circuit that has been designed by a scan method. A source electrode and a drain electrode are formed so that the recess section positions between them, a gate insulation film is formed on the surface layer and on inner-surface of the recess section including the channel layer, and a gate electrode is formed on the gate insulating film in the recess section. Other embodiments include processes for the production of CFC-217ba and HFC-227ea. The antenna can be arrayed in 1D and 2D on a single common substrate. The body’s moisture causes the plug to expand to complete the sealing of the opening, or the expansion may be caused by exposure to air, light, or other stimulant.