A method of forming an integrated circuit package with an upward-facing chip cavity such that the fabrication of the substrate and the packaging of silicon chip are combined. Each support is provided with targets that are different from each other. Addition voltage \u0394V is added to each operation unit as bias voltage, whereby a write operation can be carried out with characteristic of injected current IFG that is uniform among respective operation units duration of which are generally same. The bandlimited estimated envelope signal is then amplified by an envelope amplifier circuit.