A complementary metal oxide semiconductor low-power, high speed logic circuit consisting of a cascaded chain of stages. Methods of preparing the foams, comprising extruding the polystyrene with a novel fire retardant formulation comprising a mixture of a) a phosphate compound, preferably TPP; b) less than about 2. The chip includes a display engine that processes graphics images organized as windows. The resilient polymeric base layer, the metalized layer, and the conductive plating have an aggregate spring constant sufficient to maintain distal portions of the contact members in a cantilevered configuration and to form a stable electrical connection between the distal portions and the first circuit member solely by compressive engagement. The adjustment mechanism can be selectively operable to flex the resilient side member to move the second distal portion away from the frame and to un-flex the resilient side member to move the second distal portion toward the frame. A generated scan line may be shifted to compensate for a cross-scanning axis error.