A bus interface circuit and method for reliable data capture in the presence of bus-master changeovers andor for synchronizing received data to an internal clock signal, wherein the received data includes a strobe. The message comprises an updated subframe allocation bitmap indicating a second plurality of subframes including an updated plurality of almost blank subframes. The control signal overrides a periodic switching signal applied to the gate of the MOSFET, causing it to conduct continuously and thereby apply a shunt path for the output current of the rectifier. A timing and control circuit provides timing control voltages to the sample-and-hold circuit based on input signals associated with phase 1 and phase 2.