A power reset signal generator provides a power reset signal having a minimum predetermined pulse width independent of the ramp time of the applied power. A configuration data frame for a FPGA is loaded to the Frame register of the FPGA and also to an error detection circuit which detects errors with the loaded frame. An edge protection made of thermally stable threads is provided along the edges of the flat structure. The image is both front and back lit. The first IC includes a timing controller for providing control signals and video signals, a source driver for receiving the control signals and video signals and driving the panel, and a common voltage circuit for providing a common voltage to the panel.