An MD5 processing apparatus is a hardware-implemented MD5 process in a programmable device such as an FPGA or the like. The error amplifier inputs a voltage signal corresponding to an output voltage of a DCDC result and a plurality of reference voltage signals. On determining such an apparent failure in the primary message channel, the queue manager determines whether the secondary message channel is associated with the first transmission queue. A traversal of the bi-partite graph can be performed to expand the training data to encompass sufficient data to perform classification of the present search task. A flow control device controls the modulating devices such that the fluid flow rates in the fluid supply path and outlet path of the heat exchanger are balanced, so as to be substantially the same.