A thin film transistor array panel, according to an embodiment of the present invention, includes a first data line, a second data line neighboring the first data line, a transistor disposed in a region between the first data line and the second data line, and a pixel electrode disposed close to the second data line among the first and second data lines. One method includes mapping a data pattern to a number of program state combinations L corresponding to a group of memory cells configured to store a fractional number of data units per cell. A test kit including a specimen testing device and reagents for performing a primary test a secondary test on specimens.