An N-bit DAC comprises a main DAC circuit having main nodes on which analogue voltages are produced of progressively increasing values in steps of the value of one MSB value, and a sub-DAC circuit having secondary nodes on which analogue voltages are produced of progressively increasing values in steps of the value of one LSB. The system addresses the use of \u201cearliest-first\u201d and \u201cno-reuse\u201d policies as criteria for the correctness of counting. Each wheel is driven by an electric motor electrically connected to a power source.