A circuit layout methology is provided for eliminating the extra processing time and file-space requirements associated with the optical proximity correction of a VLSI design. The multilayer film-coated member is fabricated by coating the surface of a substrate with at least two hard coating films having different compositions, in which the first composition hard coating film of the outermost layer of the hard coating films represented by SiaBbNcCdOe with a+b+c+d+e=1, 0. In the step of forming the first metal electrode, the aluminum layer is formed so that the surface thereof satisfies a relationship of Rmax<80 nm, Rms<10 nm, and Ra<9 nm. Each process unit extends linearly in a direction substantially perpendicular to the common transfer chamber. The final core cross-section defines a fundamental mode cutoff wavelength \u03bbc such that \u03bbc\u2267\u03bbm along the axis. The method includes identifying links from linking documents to linked documents in the network and determining an importance of the identified links.