A method is provided for identifying in a computer system physical memory modules having failing or defective addresses. The test system is formed of a functional test unit for testing a digital function of a device under test, an analog test unit for testing an analog function of the DUT, and a synchronous control unit for synchronizing operations between the functional test unit and the analog test unit. In a place where the condenser plate is retractive, a part of sidewalls are exposed outside. The bypass logic is configured to selectively bypass one or more delay elements of the plurality of delay elements to provide the first bit of the delayed serialized data to the driver circuitry. Moreover, a virtual page may also be tilted about a central axis of the virtual page to accommodate viewing of a desired section on the display system.