An apparatus comprises an integrated circuit and a resistor external to the IC. The image detection unit contains a view field area that covers at least a reaction area and a background area in a test piece. To achieve these objectives, there is a disclosed computer peripheral device connected to the host computer, wherein the peripheral device is comprised of a connection signal transmitter and a controller. According to the invention, it comprises: \u2014a step of synthesis to define a parser architecture from the hardware structure; \u2014a step of processing parser operations based on the hardware architecture. Secondary signal distribution may also be enhanced, and so may be inputoutput circuitry and cascade connections between adjacent or nearby logic modules on the device.