A digital electronic device is provided with a first and second sequential logic unit, each for receiving an input signal and for outputting a first and second output signal, respectively. The processor including a second distributed shift generator associated with a second time domain, wherein the second distributed shift generator is coupled to a second group of scan chains, the second distributed shift generator to send a shift-enable-flop signal to be received by the second group of scan chains. The source lighting array comprises a plurality of lighting elements.