An integrated circuit disclosed in the present invention comprises a unit for generating an integrated voltage corresponding to a phase error between a reference voltage of a PLL circuit and a dividing signal so as to compare the generated integrated voltage with said reference voltage. In the present invention, as a wiring board on which a semiconductor chip is mounted, a build-up wiring board is not used but a through wiring board THWB is used. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench. The plasma etch resist material may be initially patterned using photolithography, electron-beam lithography or a block copolymer self-assembly process.