A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. The feasibility and effectiveness of such a framework are demonstrated using a sample application of the framework. The individual dies include integrated circuitry and a terminal electrically coupled to the integrated circuitry. Upon being granted a bus transaction on a bus channel, the corresponding weighting register is decremented by an amount that reflects the bus channel bandwidth consumed by the transaction, measured in amount of data transferred or number of bus data transfer cycles required to complete the transaction. By providing a cyclone with a wall having two portions of different sizes and a lip extending from the portion with the smaller size into the portion with the larger size, the risk of blockages due to re-entrainment and movement of dirt and dust within the cyclonic separating apparatus is reduced.