A micro-conformal nanoimprint lithography template includes a backing layer and a nanopatterned layer adhered to the backing layer. The electrical wiring device includes a device housing and at least one switch disposed within the device housing. A method for implanting a localization wire includes inserting a cannula with a preloaded localization wire into a tissue mass and relatively moving the cannula and localization wire to expose a portion of the localization wire to the tissue mass. In a further embodiment, constrained usage model comprises sending the packet in an Ethernet protocol packet over an Ethernet network, the Ethernet protocol packet having a OSI layer two header, but not a layer three header. The present invention is a circuit design that utilizes two transistor types\u2014bipolar and MOS one of which can be manufactured together with the memory cell’s non-linear conductive elements thereby reducing the number of processing steps and masks and resulting in lower cost. The TMR element portions 11A and 11B are disposed in a direction parallel with their laminated surfaces with respect to each other.