A new method of designing digital filters for specific magnitude and phase requirements that minimises the filter’s group-delay given arbitrary error tolerances is presented in this patent application. The computer comprises a processor coupled through a system bus to IO devices and to a system memory, the computer further having a basic input output system unit operatively coupled to the system bus for loading a computer operating system during a computer boot procedure, wherein the system memory being accessible to the computer operating system via the system bus. During a call process, the system keeps updating the service rate allocated to meet the QoS requirement of a new flow request, the updated service rate being allocated to a new flow request of the same type.