A new, useful, and non-obvious shader processor architecture having a shader register file that acts both as an internal storage register file for temporarily storing data within the shader processor and as a First-In First-Out buffer for a subsequent module. Accordingly, with the present invention implemented, delays in neighbor cell SCH decoding and signal level measurement are significantly reduced and may thus no longer result in incomplete data for inter-cell handover decision or even unsuccessfull handovers. One or more magnets, which may be static or moving, may be included within the re-entrant vessel.