The present invention provides a semiconductor device wherein the area of a peripheral circuit region with respect to a pixel region is reduced, and provides a manufacturing method of the semiconductor device. The body portion of one member at least partially overlaps the opening in the second member to create a joined opening. A test plate for holding DUTs includes such a ceramic layer that provides better wear while enabling use of the base as a guard layer during testing. The three-phase hydroprocessing zone comprises one or more single-liquid-pass catalyst beds disposed in a trickle bed reactor. A primary winding of a transformer, the switching circuit, and the secondary windings are disposed on the primary region.