A mechanism is provided for dynamic cache allocation using bandwidth. The first and the second bearing surfaces form a hydrodynamic bearing. The resistor network is configured to provide a ratio signal that indicates an amount to delay data bit signals associated with a data group. The wafer holder diameter is 63 to 73 percent of the wafer diameter, and the surface roughness Ra of the portion of the wafer holder in contact with the wafer is set from 1 \u03bcm to 1,000 \u03bcm.