A system and method for detecting a defect in a transistor array includes applying a test signal to the array, monitoring pixel voltage along a gate line of the array, and detecting a defect associated with the gate line based on a variation in the pixel voltage during the monitoring step. In addition, in the first elementary stage a first switching element is arranged between the first transfer node and the second transfer node, has a control terminal receiving a control signal, and is closed during a charge-transfer interval; and first charge-storage means are connected between the control terminal and the first phase input. Numerous other aspects are provided. 20 nm and a pore volume of pores having a pore diameter calculated according to a Cranston-Inkley method of 5. Nonvolatile memory elements store the test results in a buffer.