A method and apparatus for controlling program instruction completion timing for processor verification provides, alternatively or in combination, an improved simulation technique andor processor in which resource allocation as well as other performance-specific scenarios can be stressed over typical operating conditions by controlling the completion timing of one or more program instructions. The system comprises a number of user input stations for entering a shipping request. A layer having wavelength conversion material provided therein is disposed over the array of LED chips for forming a light emitting surface from which light is emitted upon activation of the LED chips.