A lamination ceramic chip inductor includes at least one pair of insulation layers; and at least one conductive pattern which is interposed between the at least one pair of insulation layers and forming a conductive coil. A non-destructive sense node is connected to an output of the horizontal shift register. When the CPU is in abnormal and the manual operation on the mechanical switch reaches a preset time, the delay circuit is activated to control the second switch to be in an \u201con\u201d state or in an \u201coff\u201d state to control the first switch to be in the \u201coff\u201d state. The interface state data bus section is in communication with: both the at least one front-end one and the at least one rear-end one of the directors; and to the memory. The groove has a depth that will accept the pawls when they are bent inward. The plank member is of hollow cross-section and incorporates at least one internal longitudinal web disposed parallel to the upper, load bearing surface of the plank member, the web being spaced from the underside of the plank member by a distance less than the length of said peg members.