A semiconductor memory device includes a plurality of address pins for receiving a plurality of address signals from a chipset, and an address strobe pin for receiving an address strobe signal from the chipset. A central region has a first thickness range that is thicker than the thickness range of any of the other regions. An armature core with a plurality of pole teeth is radially formed and a coil is wound up in each of the pole teeth. The system also establishes a significance level, calculates the test statistic, and generates an output. A recognize process is then used to recognize freeze moments when current decisions may need to be re-considered.