A nonvolatile memory device may include a memory cell array adapted to store tail-bit flag information indicating tail-bit memory cells, and a tail-bit controller adapted to calibrate a program start voltage of normal memory cells and a program start voltage of the tail-bit memory cells independently based upon the tail-bit flag information. During reads from the disk, the disk controller uses a traditional logical track layout and logical block address numbering having a track skew value related to read settle time. The grid array architecture includes an electrode structure with an anode layer, a cathode layer and a thermistor layer. Accordingly, the semiconductor memory device including the IOSA controller may safely test a characteristic of the IOSA.