A method for reducing wafer backside large particle contamination, comprising: performing front end of line processing of a memory device, depositing a thick oxide on the wafer backside so that at least pre-selected oxide thickness remains after back end of line processing is complete and performing the back end of line processing of the memory device. The circuit has a first metallization layer becoming gate electrodes and gate interconnections. The exposed, continuous surface is affixed to the grid of sense elements. A selection of an additional transaction is received after initiation of one of the selected transactions but before completion of all of the selected transactions. The second exit path guides a sheet to the second sheet outlet tray.