Provided are a DLL circuit having a coarse lock time adaptive to a frequency band of an external clock signal and a semiconductor memory device having the DLL circuit. Whether to perform adjustment processing is determined based on determination of an image forming condition. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6HCl or SF6Cl2 can form the edge profile of contact holes to be smoothed. In other embodiments, the semiconductor package includes a substrate with multiple layers; a die coupled to the first of the layers; an electrical connector coupled to the final layer; and a spiral trace, in or on the substrate.