1461121641-d11cceab-f535-48ec-a677-a615d07abc7a

A top-gate molding system for encapsulating semiconductor devices includes a plurality of mold cavities formed between a middle plate and a bottom plate, and a runner system formed between an upper plate and the middle plate. It further comprises a proper-assembly indicator for checking that the clip is properly assembled in the cramping position, said proper-assembly indicator being in the form of a sort of stud that is constrained to retract under the effect of the cramping face retracting so as to be able to start being pushed into the clip. Due to the integration of the logic dies and the memory dies, the reconfigurable logic device can perform various data manipulation operations with higher bandwidth and lower latency and power consumption compared to devices external to the die-stacked memory device. Similarly, the intermediate zone minimizes deformation of the outer zone from a radial deflection of the inner zone by absorbing at least some of the deformation. The power saving techniques may utilize different modulation schemes, different throughputs, different symbol rates, or other techniques. The invention is also directed to pharmaceutical compositions comprising these compounds and the use of these compounds and compositions in the treatment of such diseases in which the beta-secretase enzyme is involved.