A system and method for efficient improvement of timing analysis for faster processor designs with negligible impact on die-area. The connecting means each have a connecting plane, into which the outlets open, each covered by a protective means, and which are movable into engagement with each other with the outlets facing each other. The wall blocks are configured such that the at least one continuous passageway is formed when a plurality of blocks are laid side by side in a tier and stacked one atop of another to form an additional tier. The HECI simulator intercepts commands directed to the HECI driver from software running on the remote computer system and routes the commands as HECI messages to a local computer system also included in the system.