A redundant link management switch for use in a stack of switches forming a closed-loop link topology, including a stacking module, a processor and a management module. Endpoints with excessive latency are identified as having a delay. With regard to the second p-ch TFT P2, a gate thereof is connected to the second capacitor C2, a source thereof is connected to a third capacitor C3, and a drain thereof is connected to the first capacitor C1. The at least one MP sends a channel change response message to the CM. Each of the adhesive grids 108, 110 is augmented by a respective continuous ribbon of adhesive 112, 114 along the entire perimeter of each respective interface between the VIP 102 and each respective cover board 104, 106.