A high-speed differential signaling logic gate includes a 1st input transistor, 2nd input transistor, complimentary transistor, current source, a 1st load, and a 2nd load. The first and second sensors are positioned in the reservoir. The Enterlink bus uses, for the first time, metachannels, a metachannel engine and a metachannel repository Connectors connect the Enterlink public process applications and the company private I process applications with the bus. An aging process can indicate which nodes have not been recently invoked.