1460403491-e254b9f6-b0e2-4336-914d-152afdff7b25

A bit-serial multiplier and an infinite impulse response filter implemented therewith, both implemented on an FPGA, are described in various embodiments. By using overhead bytes as extended APS node IDs, large single ring SONETSDH systems can be avoided. The seal element is made of a heat insulative material and is arranged between the case and the hot plate.