Disclosed are various embodiments of voltage protectors that include a first voltage clamping device configured to clamp a voltage of an input power applied to an electrical load, and a second voltage clamping device configured to clamp the voltage applied to the electrical load. In a preferred case, the hydrogel precursors are poly diacrylate and N-isopropylacrylamide and the continuous phase of the emulsion is an aqueous solution of dextran and a dextran solubility reducer. At least one of circuit elements constituting the latch circuit is located above the access transistor. The specific digital value is associated with the particular memory address received form the host. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.