A timing-driven layout method is provided, which realizes timing error convergence toward zero without any timing constraint file. The other processors enter the debug mode as a result of the one processor asserting a debug event signal upon initially entering the debug mode. The filler is preferably clay, exemplified by montmorillonite and chlorite. The doped depletion regions have an impurity concentration and thickness so that the doped depletion regions are depleted due to a built-in potential creatable between the doped depletion regions and the substrate. An RFID tag includes an antenna pad, a receiver, a state machine, and a modulator.