A flash memory cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate proximate the main surface and a drain region in a portion of the silicon substrate proximate the main surface. A lock surface 43 inclining to a radial direction of the piston rod 18 is formed in an engagement member 31 provided in the piston rod 18. The shaping filter is configured so that the product of the pulse transfer function of the two-degree-of-freedom repetitive compensator and the complementary sensitivity function of a general-purpose control system has a low-pass characteristic. The interleaver receives the input bits sequentially by row.